1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device having an effective channel length specified by the difference in diffusion length between two impurities of different conductivity types, and a method of manufacturing the same.
2. Description of the Background Art
MOSFETs formed by the DSA (Diffusion Self-Align) process are referred to as DMOS transistors. A DMOS transistor is one of the semiconductor devices having an effective channel length specified by the difference in diffusion length between two impurities of different conductivity types.
FIG. 16 shows a cross-sectional structure of a background art DMOS transistor 80. As shown in FIG. 16, the DMOS transistor 80 comprises a semiconductor body BD including a semiconductor substrate 1 containing an n-type impurity of a relatively high concentration (n.sup.+), and an epitaxial layer 2 formed on the semiconductor substrate 1 and containing an n-type impurity of a relatively low concentration (n.sup.-).
A first semiconductor region 3 containing a p-type impurity and a pair of second semiconductor regions 5 containing an n-type impurity of a relatively high concentration are double diffused in an upper main surface of the epitaxial layer 2. The pair of second semiconductor regions 5 are selectively formed in predetermined spaced apart relationship in the first semiconductor region 3. A source electrode 11 is formed on respective edges (referred to as first edges) of the pair of second semiconductor regions 5 which are opposed to each other and on an upper surface of part of the first semiconductor region 3 which lies between the pair of second semiconductor regions 5.
A deep semiconductor region 4 containing a p-type impurity of a relatively high concentration (p.sup.+) is formed in partially overlapping relationship with the first semiconductor region 3 and extends to a deeper position than the first semiconductor region 3.
A pair of gate insulation films 6 are formed on the first semiconductor region 3 outside of respective edges (referred to as second edges) of the pair of second semiconductor regions 5 which are on the opposite sides from the first edges and on the upper main surface of the epitaxial layer 2. A pair of gates 7 are formed on the gate insulation films 6, respectively. Part of the first semiconductor region 3 which lies immediately under each of the gates 7 serves as a channel region when the device is in operation.
Isolating insulation films 10 are formed to cover the upper and side surfaces of the gates 7 and the upper surface of the second semiconductor regions 5. The isolating insulation films 10 are provided for electric isolation between the gates 7 and the source electrode 11.
A drain electrode 12 is formed on the opposite main surface of the semiconductor substrate 1 from the epitaxial layer 2.
In FIG. 16, electric connections between the gates 7, the source electrode 11 and the drain electrode 12 are shown in diagrammatic form, and respective terminals thereof are designated by the reference characters G, S and D.
In the DMOS transistor 80 with such an arrangement, the length of the second semiconductor regions 5 as measured in the direction of a main current flow is specified by an isolation margin between each of the gates 7 and the source electrode 11 and the length of a contact between the source electrode 11 and each of the second semiconductor regions 5. This will be described with reference to a partial view of the DMOS transistor 80 shown in FIG. 17.
The length a of the second semiconductor region 5 as shown in FIG. 17 is substantially determined by the sum of the isolation margin b between the gate 7 and the source electrode 11 and the contact length c between the source electrode 11 and the second semiconductor region 5.
The isolation margin b is set at a length determined in consideration for mask alignment precision and the like during manufacture to prevent a fault resulting from a short circuit between the gate 7 and the source electrode 11. The contact length c is set so that a predetermined contact resistance is provided between the source electrode 11 and the second semiconductor region 5. Both of the isolation margin b and the contact length c are not permitted to be extremely short.
FIG. 18 shows an equivalent circuit of the DMOS transistor 80. As shown in FIG. 18, the DMOS transistor 80 comprises the epitaxial layer 2, the first semiconductor region 3, the second semiconductor region 5, and the gate 7. The DMOS transistor 80 further has a parasitic NPN transistor T1 comprised of the epitaxial layer 2, the first semiconductor region 3 and the second semiconductor region 5, and a resistance element R1 depending on the length of the second semiconductor region 5 (as measured in the direction of the main current flow) and present in the first semiconductor region 3 under the second semiconductor region 5 which serves as a hole current path.
A hole current flow into the resistance element R1 develops a potential equivalent to the product of the hole current and the resistance element R1. FIG. 19 schematically shows a flow of hole current HL and a flow of electron current EL.
When the increasing hole current causes the potential resulting from the resistance element R1 to exceed a built-in potential (about 0.7 V) of a pn junction, the parasitic NPN transistor T1 turns ON to cause a very large current to flow into the DMOS transistor 80, resulting in breakdown of the DMOS transistor 80. To prevent such a situation, it is necessary to limit a drain current to prevent the increase in hole current. This results in the decrease in current area (safe operating area) in which the DMOS transistor 80 operates safely.
An example of the background art DMOS transistors includes a DMOS transistor 90 having a cross-sectional structure shown in FIG. 20. The DMOS transistor 90 shown in FIG. 20 is constructed such that a source electrode 11 contacts side surfaces of a pair of second semiconductor regions 5 at their respective edges (referred to as first edges) opposed to each other, and the side and bottom surfaces of a recessed portion RC formed in the first semiconductor region 3 between the pair of second semiconductor regions 5. Like reference numerals and characters are used to designate constituents identical with those of the DMOS transistor 80 shown in FIG. 16, and the description thereon will be dispensed with.
The DMOS transistor 90 in which the source electrode 11 contacts the side surfaces of the second semiconductor regions 5 is not required to bring the source electrode 11 into contact with the main surface of the second semiconductor regions 5. Thus, the length of the second semiconductor regions 5 (as measured in the direction of the main current flow) is specified only by the isolation margin between each of the gates 7 and the source electrode 11. Therefore, the length of the second semiconductor regions 5 of the DMOS transistor 90 is less than that of the DMOS transistor 80 shown in FIG. 16. Further, the decrease in the isolation margin may further shorten the length of the second semiconductor regions 5 to decrease the resistance element under each of the second semiconductor regions 5 to increase the safe operating current area. FIG. 21 schematically shows flows of hole current HL and electron current El, and a resistance element R2 under the second semiconductor region 5 in the DMOS transistor 90.
However, the decrease in the isolation margin increases the rate of faults resulting from a short circuit between the gate 7 and the source electrode 11, and involves the need for a high-precision mask alignment process step to deal with the decreased isolation margin. The use of manufacturing equipment to solve the above-mentioned problems adds to manufacturing costs.